1. Field of the Invention
The present invention relates to frequency dividers, and more particularly to a frequency divider capable of reducing jitter and power consumption.
2. Description of the Prior Art
In many applications, a precise output frequency is often generated by a fractional-N frequency divider based on a reference frequency. Whereas an integer-N frequency divider may only generate the output period as an integer multiple of the reference period, e.g. 4 times the reference period, the fractional-N frequency divider may generate fractional multiples of the reference period, such as 4.01 times the reference period. By switching from divide by M to divide by M+1 upon detection of a carry signal or overflow signal, the fractional-N frequency divider is capable of synthesizing frequencies which are a fractional multiple of the reference frequency. For example, the fractional-N frequency divider may output the output frequency as 0.3 times the reference frequency by dividing by 3 in two cycles of a group of three cycles, then dividing by 4 in a remaining one cycle of the group of three cycles.
The fractional-N frequency divider has a complicated circuit design, which has problems of high power consumption, large chip area, and jitter performance.